1. Field of the Invention
The present invention relates to techniques for improving computer system performance. More specifically, the present invention relates to a method and an apparatus for supporting inter-process communication through use of a conditional trap instruction.
2. Related Art
As increasing semiconductor integration densities allow more transistors to be integrated onto a microprocessor chip, computer designers are investigating different methods of using these transistors to increase computer system performance. Some recent computer architectures exploit xe2x80x9cinstruction level parallelism,xe2x80x9d in which a single central processing unit (CPU) issues multiple instructions in a single cycle. Given proper compiler support, instruction level parallelism has proven effective at increasing computational performance across a wide range of computational tasks. However, inter-instruction dependencies generally limit the performance gains realized from using instruction level parallelism to a factor of two or three.
Another method for increasing computational speed is xe2x80x9cspeculative executionxe2x80x9d in which a processor executes multiple branch paths simultaneously, or predicts a branch, so that the processor can continue executing without waiting for the result of the branch operation. By reducing dependencies on branch conditions, speculative execution can increase the total number of instructions issued.
Unfortunately, conventional speculative execution typically provides a limited performance improvement because only a small number of instructions can be speculatively executed. One reason for this limitation is that conventional speculative execution is typically performed at the basic block level, and basic blocks tend to include only a small number of instructions. Another reason is that conventional hardware structures used to perform speculative execution can only accommodate a small number of speculative instructions.
What is needed is a method and apparatus that facilitates speculative execution of program instructions at a higher level of granularity so that many more instructions can be speculatively executed.
One challenge in designing a system that supports speculative execution is to provide an efficient mechanism for communication between speculative threads and other threads in the computer system. Conventional shared memory communication mechanisms are typically slow and inefficient, because accesses to shared variables require time-consuming load operations, and can sometimes cause cache lines to ping-pong back and forth between caches. Slow communications are particularly a problem for frequently executed communication operations. For example, a speculative thread may have to communicate frequently with a non-speculative thread in order to determine when to perform a join operation to merge the state of the speculative thread into the state of the non-speculative thread. If these frequent communications are too slow, the performance advantages of speculative execution can be lost.
Hence, what is needed is a method and an apparatus that facilitates efficient inter-process communications in a multiprocessor system to support speculative execution.
One embodiment of the present invention provides a system that supports inter-process communication through use of a conditional trap instruction. The system operates by allowing a first process to send a communication to a second process by writing to a register that is visible to the second process. The second process then examines a value in the register by executing the conditional trap instruction to examine the value in the register. If the value in the register satisfies a condition specified by the conditional trap instruction, the system executes a trap handling routine that takes an action in response to the communication from the first process. If the value in the register does not satisfy the condition, the system takes no action and proceeds with execution of the code.
In one embodiment of the present invention, the first process writes to the register by causing an interrupt that writes to the register.
In one embodiment of the present invention, the first process is a head thread and the second process is a speculative thread that speculatively executes program instructions in advance of the head thread while the head thread is executing. In this embodiment, the head thread communicates with the speculative thread in order to inform the speculative thread that the speculative thread can perform a join operation with the head thread. In a variation on this embodiment, the system keeps track of how many locks the speculative thread is holding, and executes the conditional trap instruction only if the speculative thread is holding no locks. In this way, the speculative thread only performs the join operation when the speculative thread is holding no locks.
In one embodiment of the present invention, the conditional trap instruction is located within code that implements a monitor exit operation.
In one embodiment of the present invention, the register is a processor status register within a processor on which the second process is running. In this embodiment, the conditional trap instruction examines a conditional trap bit in the processor status register.
In one embodiment of the present invention, the first process and the second process execute on different processors within a multi-processor system.
In one embodiment of the present invention, the conditional trap instruction is located within a very long instruction word (VLIW) instruction.
In one embodiment of the present invention, the conditional trap instruction is a bounds check instruction.